| commit | d87576e38df760ef1cb635197d51f207e2a8eda9 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 27 Jan 2017 15:20:25 +0000 (27 15:20 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 27 Jan 2017 15:29:08 +0000 (27 15:29 +0000) | ||
| tree | d0cb56d4a824b42706ae2056cdf71be6539dd749 | treesnapshot (tar.gz zip) |
| parent | e62694a078f182c822a7b6d3976b1bcc72e78ec2 | commitdiff |
arm_gicv3: Fix broken logic in ELRSR calculation
Fix a broken expression in the calculation of ELRSR
register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
we want to check for != 0, because the HW bit is not
bit 0 so a test for == 1 is always false.
Fixes: https://bugs.launchpad.net/bugs/1658506
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
Fix a broken expression in the calculation of ELRSR
register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
we want to check for != 0, because the HW bit is not
bit 0 so a test for == 1 is always false.
Fixes: https://bugs.launchpad.net/bugs/1658506
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
| hw/intc/arm_gicv3_cpuif.c | diffblobblamehistory |