| commit | cc27ed81cf11d5b7ffc7eca9f31dfcd82c983c56 | |
| author | Eric Auger <eric.auger@redhat.com> | |
| Tue, 26 Jun 2018 16:50:42 +0000 (26 17:50 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 26 Jun 2018 16:50:42 +0000 (26 17:50 +0100) | ||
| tree | a56b706f73b4a109ec7d786848cddd8fcac32606 | treesnapshot (tar.gz zip) |
| parent | 32cfd7f39e0811036efd3a7a12d0f975ef57fdb3 | commitdiff |
hw/arm/smmuv3: IOTLB emulation
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256.
It is implemented as a hash table whose key is a combination
of the 16b asid and 48b IOVA (Jenkins hash).
Entries are invalidated on TLB invalidation commands, either
globally, or per asid, or per asid/iova.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1529653501-15358-4-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256.
It is implemented as a hash table whose key is a combination
of the 16b asid and 48b IOVA (Jenkins hash).
Entries are invalidated on TLB invalidation commands, either
globally, or per asid, or per asid/iova.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1529653501-15358-4-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/smmu-common.c | diffblobblamehistory | |
| hw/arm/smmuv3.c | diffblobblamehistory | |
| hw/arm/trace-events | diffblobblamehistory | |
| include/hw/arm/smmu-common.h | diffblobblamehistory |