target/loongarch: Separate the hardware flags into MMU index and PLV
commitc8885b8839dfe39ee7b02dedcbf79af9087c9079
authorRui Wang <wangrui@loongson.cn>
Mon, 7 Nov 2022 02:45:25 +0000 (7 10:45 +0800)
committerSong Gao <gaosong@loongson.cn>
Mon, 7 Nov 2022 02:54:08 +0000 (7 10:54 +0800)
tree69bb7deb7554c8ac5ffb27e536f0da51f1203e6a
parent466e81ff12013d026e2d0154266fce82bce2ee9b
target/loongarch: Separate the hardware flags into MMU index and PLV

Regarding the patchset v3 has been merged into main line, and not
approved, this patch updates to patchset v4.

Fixes: b4bda200 ("target/loongarch: Adjust the layout of hardware flags bit fields")
Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221107024526.702297-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
target/loongarch/cpu.h
target/loongarch/insn_trans/trans_privileged.c.inc
target/loongarch/tlb_helper.c
target/loongarch/translate.c
target/loongarch/translate.h