| commit | bc7a45ab88281bbced8ebe9fb87d518102b22519 | |
| author | Paul A. Clarke <pc@us.ibm.com> | |
| Wed, 18 Sep 2019 14:31:22 +0000 (18 09:31 -0500) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Fri, 4 Oct 2019 00:25:23 +0000 (4 10:25 +1000) | ||
| tree | 15b3077a2beb005d490bfe320de33cfb499cccf4 | treesnapshot (tar.gz zip) |
| parent | a2735cf483814b1c0e5773eee4a52f8e32d438cf | commitdiff |
ppc: Add support for 'mffsce' instruction
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.
On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.
On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/translate/fp-impl.inc.c | diffblobblamehistory | |
| target/ppc/translate/fp-ops.inc.c | diffblobblamehistory |