| commit | b89de436ff63218d31122b2176f7785b0628b3c6 | |
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | |
| Fri, 2 Nov 2018 13:19:12 +0000 (2 14:19 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 2 Nov 2018 14:10:53 +0000 (2 14:10 +0000) | ||
| tree | dc2a6720ab32385c4c5549494d9044dcd2f98cad | treesnapshot (tar.gz zip) |
| parent | 0f8d06f16c9d1041d728d09d464462ebe713c662 | commitdiff |
hw/arm: versal: Add a model of Xilinx Versal SoC
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| default-configs/aarch64-softmmu.mak | diffblobblamehistory | |
| hw/arm/Makefile.objs | diffblobblamehistory | |
| hw/arm/xlnx-versal.c | [new file with mode: 0644] | blob |
| include/hw/arm/xlnx-versal.h | [new file with mode: 0644] | blob |