| commit | b6889c5ae3895cf5a4322adb32b2133e9b91d158 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 10 May 2021 19:08:39 +0000 (10 20:08 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 25 May 2021 15:01:43 +0000 (25 16:01 +0100) | ||
| tree | 805365fadaeaade349c681f09aedca38cb36bcff | treesnapshot (tar.gz zip) |
| parent | 382c7160d1cd9e815fb94d3889a5ddcf0e1845ab | commitdiff |
hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524
The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model
it that way in hw/arm/armsse.c (along with the associated MPCs). We
incorrectly also added an entry to the RAMInfo array for the AN524 in
hw/arm/mps2-tz.c, which was pointless because the CPU would never see
it. Delete it.
The bug had no guest-visible effect because devices in the SSE-200
take priority over those in the board model (armsse.c maps
s->board_memory at priority -2).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-2-peter.maydell@linaro.org
The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model
it that way in hw/arm/armsse.c (along with the associated MPCs). We
incorrectly also added an entry to the RAMInfo array for the AN524 in
hw/arm/mps2-tz.c, which was pointless because the CPU would never see
it. Delete it.
The bug had no guest-visible effect because devices in the SSE-200
take priority over those in the board model (armsse.c maps
s->board_memory at priority -2).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-2-peter.maydell@linaro.org
| hw/arm/mps2-tz.c | diffblobblamehistory |