| commit | b4d3978c2fdf944e428a46d2850dbd950b6fbe78 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 13 Aug 2015 10:26:22 +0000 (13 11:26 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 13 Aug 2015 10:26:22 +0000 (13 11:26 +0100) | ||
| tree | cad66422e4c81b720274cec302bcc5eda6c471af | treesnapshot (tar.gz zip) |
| parent | 49a661910c1374858602a3002b67115893673c25 | commitdiff |
target-arm: Add the AArch64 view of the Secure physical timer
On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1437047249-2357-2-git-send-email-peter.maydell@linaro.org
| target-arm/cpu-qom.h | diffblobblamehistory | |
| target-arm/cpu.c | diffblobblamehistory | |
| target-arm/cpu.h | diffblobblamehistory | |
| target-arm/helper.c | diffblobblamehistory |