target/mips: Add Loongson-3 CPU definition
commitaf868995e1b7641577300d1342ede452ef0c5565
authorHuacai Chen <zltjiangshi@gmail.com>
Tue, 2 Jun 2020 02:39:15 +0000 (2 10:39 +0800)
committerAleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Tue, 9 Jun 2020 15:32:45 +0000 (9 17:32 +0200)
treead3cc1a541f045d6cf0acedc38209043ab3fee7c
parent9579f7816855757c747f9428a8e53d0fe0a0e9b7
target/mips: Add Loongson-3 CPU definition

Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:

1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
   suitable for TCG because Loongson-3A R1 has fewest ASE.
2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
   suitable for KVM because Loongson-3A R4 has the VZ ASE.

Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.

[AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
improved commit message, fixed checkpatch warnings]

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
target/mips/Makefile.objs
target/mips/cpu.h
target/mips/internal.h
target/mips/lmmi_helper.c [moved from target/mips/lmi_helper.c with 100% similarity]
target/mips/mips-defs.h
target/mips/translate.c
target/mips/translate_init.inc.c