| commit | af1c259f6d4f1c6b0af22a0ff0b764c4ef3ef85e | |
| author | Sandipan Das <sandipan@linux.vnet.ibm.com> | |
| Fri, 6 Oct 2017 06:42:44 +0000 (6 12:12 +0530) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 16 Oct 2017 23:34:00 +0000 (17 10:34 +1100) | ||
| tree | c35aef8362fa07c002f014c4866070cf8c6bc2e7 | treesnapshot (tar.gz zip) |
| parent | 1ed9c8af501f8d1bdf5a8725a038527be059f54d | commitdiff |
target/ppc: Fix carry flag setting for shift algebraic instructions
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
For POWER ISA v3.0, the XER bit CA32 needs to be set by the shift
right algebraic instructions whenever the CA bit is to be set. This
change affects the following instructions:
* Shift Right Algebraic Word (sraw[.])
* Shift Right Algebraic Word Immediate (srawi[.])
* Shift Right Algebraic Doubleword (srad[.])
* Shift Right Algebraic Doubleword Immediate (sradi[.])
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/int_helper.c | diffblobblamehistory | |
| target/ppc/translate.c | diffblobblamehistory |