| commit | a97d3c18f61fd307bffd3579ba35fccd2d88aeb1 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 19 Jun 2023 10:20:21 +0000 (19 11:20 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 19 Jun 2023 10:22:18 +0000 (19 11:22 +0100) | ||
| tree | 5640e8cf031dd65d1c55f78d684c29de61bda26e | treesnapshot (tar.gz zip) |
| parent | 6e3c8049ad90951e81077d594f2cfe8c10047213 | commitdiff |
target/arm: Convert exception generation instructions to decodetree
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document the patterns in a64.decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document the patterns in a64.decode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
| target/arm/tcg/a64.decode | diffblobblamehistory | |
| target/arm/tcg/translate-a64.c | diffblobblamehistory |