| commit | a89ff39ee9016613356677941d8f70be40e06cc3 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 2 Jun 2017 10:51:47 +0000 (2 11:51 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 2 Jun 2017 10:51:47 +0000 (2 11:51 +0100) | ||
| tree | 26e8f69431c787d472c255b2b9df10417f22dce6 | treesnapshot (tar.gz zip) |
| parent | 8193d4617cfdaec6e95c2087d9a13197dc261ef0 | commitdiff |
hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1
When we calculate the mask to use to get the group priority from
an interrupt priority, the way that NS BPR1 is handled differs
from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
the group priority is in bits [7:1], whereas for BPR0 and S BPR1
this is indicated by a 0 BPR value.
Subtract 1 from the BPR value before creating the mask if
we're using the NS BPR value, for both hardware and virtual
interrupts, as the GICv3 pseudocode does, and fix the comments
accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org
When we calculate the mask to use to get the group priority from
an interrupt priority, the way that NS BPR1 is handled differs
from how BPR0 and S BPR1 work -- a BPR1 value of 1 means
the group priority is in bits [7:1], whereas for BPR0 and S BPR1
this is indicated by a 0 BPR value.
Subtract 1 from the BPR value before creating the mask if
we're using the NS BPR value, for both hardware and virtual
interrupts, as the GICv3 pseudocode does, and fix the comments
accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493226792-3237-4-git-send-email-peter.maydell@linaro.org
| hw/intc/arm_gicv3_cpuif.c | diffblobblamehistory |