| commit | a859595791e6ac5c14afe0b8a53634bf1cc21f0f | |
| author | François Baldassari <francois@pebble.com> | |
| Thu, 19 Nov 2015 12:09:52 +0000 (19 12:09 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 Nov 2015 12:09:52 +0000 (19 12:09 +0000) | ||
| tree | 30cfcf1079763b0422c399d9db0af363437d07b5 | treesnapshot (tar.gz zip) |
| parent | 8f280309030331a912fd8924c129d8bd59e1bdc7 | commitdiff |
hw/arm_gic: Correctly restore nested irq priority
Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.
Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.
Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/arm_gic.c | diffblobblamehistory |