target/arm: Hoist address increment for vector memory ops
commita7d8143aed2268f147cc1abfebc848ed6282a313
authorRichard Henderson <rth@twiddle.net>
Wed, 24 Oct 2018 06:50:18 +0000 (24 07:50 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Wed, 24 Oct 2018 06:51:36 +0000 (24 07:51 +0100)
tree151e47041dac78e03eb1f0ff08a2be7b2a60aca0
parentea358872a6a2e136a6a2bc08649a079acb99b6a2
target/arm: Hoist address increment for vector memory ops

This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).

Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 20181011205206.3552-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c