| commit | a50fe66846d1d02065265f1e54c2b0007f8cb609 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 18 May 2020 14:03:09 +0000 (18 16:03 +0200) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 21 May 2020 21:05:27 +0000 (21 22:05 +0100) | ||
| tree | 1e25486165f305f3873f4d7d8d2736d84d0942fd | treesnapshot (tar.gz zip) |
| parent | 492edf3e3038760aa6b7eb6a9bfdb648d4fa9b80 | commitdiff |
hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.
When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
the default value on the APB bus is 0.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200518140309.5220-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.
When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
the default value on the APB bus is 0.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200518140309.5220-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/timer/exynos4210_mct.c | diffblobblamehistory |