| commit | a21993c7f98862823280d1eb6d3e93cf6267896f | |
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | |
| Fri, 5 Mar 2021 13:06:38 +0000 (5 14:06 +0100) | ||
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | |
| Sun, 14 Mar 2021 13:49:01 +0000 (14 14:49 +0100) | ||
| tree | 95cba878e0753b1816e70c6f5a47de812d0e0416 | treesnapshot (tar.gz zip) |
| parent | 007479842b27e03173a333b8c2e0dae14be64f8d | commitdiff |
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| target/tricore/translate.c | diffblobblamehistory |