| commit | a1bb73849fbd7d992b6ac2cf30c034244fb2299d | |
| author | Scott Wood <scottwood@freescale.com> | |
| Fri, 21 Dec 2012 16:15:41 +0000 (21 16:15 +0000) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Mon, 7 Jan 2013 16:37:10 +0000 (7 17:37 +0100) | ||
| tree | 4cfda2d8b0e6a53b5b34c386734147b5f693bbb8 | treesnapshot (tar.gz zip) |
| parent | e99fd8af63a1692a1159cba8fa4943f2589adf97 | commitdiff |
ppc/booke: fix crit/mcheck/debug exceptions
Book E does not play games with certain bits of xSRR1 being MSR save
bits and others being error status. xSRR1 is the old MSR, period.
This was causing things like MSR[CE] to be lost, even in the saved
version, as soon as you take an exception.
rfci/rfdi/rfmci are fixed to pass the actual xSRR1 register contents,
rather than the register number.
Put FIXME comments on the hack that is "asrr0/1". The whole point of
separate exception levels is so that you can, for example, take a machine
check or debug interrupt without corrupting critical-level operations.
The right xSRR0/1 set needs to be chosen based on CPU type flags.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Book E does not play games with certain bits of xSRR1 being MSR save
bits and others being error status. xSRR1 is the old MSR, period.
This was causing things like MSR[CE] to be lost, even in the saved
version, as soon as you take an exception.
rfci/rfdi/rfmci are fixed to pass the actual xSRR1 register contents,
rather than the register number.
Put FIXME comments on the hack that is "asrr0/1". The whole point of
separate exception levels is so that you can, for example, take a machine
check or debug interrupt without corrupting critical-level operations.
The right xSRR0/1 set needs to be chosen based on CPU type flags.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/excp_helper.c | diffblobblamehistory |