target/mips: Introduce 32 R5900 multimedia registers
commita168a796e1c251787fcdf2d9ca1e9e69cb86ffcd
authorFredrik Noring <noring@nocrew.org>
Thu, 17 Jan 2019 17:44:05 +0000 (17 18:44 +0100)
committerAleksandar Markovic <amarkovic@wavecomp.com>
Fri, 18 Jan 2019 15:53:28 +0000 (18 16:53 +0100)
tree3ce5635f8ee58d3e45ee71d21c1c325d62a7020b
parent294fc2ea7f8af913523bf004433704377d9ee7a8
target/mips: Introduce 32 R5900 multimedia registers

The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
target/mips/cpu.h
target/mips/translate.c