| commit | 9febd175415dbc84e6ff7bda9bf6d90fe060181e | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 19 Feb 2021 14:46:05 +0000 (19 14:46 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 8 Mar 2021 17:20:03 +0000 (8 17:20 +0000) | ||
| tree | 327e6c25c170d1c7a716139ce7df0ad9926f4362 | treesnapshot (tar.gz zip) |
| parent | 1aa9e174b4b8de9ea52f9583c476e295065b96e3 | commitdiff |
hw/arm/armsse: Add support for SSE variants with a system counter
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has the counter in a different location.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-33-peter.maydell@linaro.org
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has the counter in a different location.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-33-peter.maydell@linaro.org
| hw/arm/armsse.c | diffblobblamehistory | |
| include/hw/arm/armsse.h | diffblobblamehistory |