| commit | 9f61763574fb19525a68c46f3b8f763e5936a6fe | |
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | |
| Mon, 8 Mar 2021 22:46:36 +0000 (8 23:46 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 12 Mar 2021 12:40:09 +0000 (12 12:40 +0000) | ||
| tree | 0465fcd543f6de9b77c45baf86cdb4184ee287be | treesnapshot (tar.gz zip) |
| parent | 6f34661b6c97a37a5efc27d31c037ddeda4547e2 | commitdiff |
hw/misc: versal: Add a model of the XRAM controller
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/misc/meson.build | diffblobblamehistory | |
| hw/misc/xlnx-versal-xramc.c | [new file with mode: 0644] | blob |
| include/hw/misc/xlnx-versal-xramc.h | [new file with mode: 0644] | blob |