| commit | 9c6f933e71ccfde036d7e19c1ddc2b1a82cc45c0 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 12 May 2022 15:14:53 +0000 (12 16:14 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 May 2022 15:19:02 +0000 (19 16:19 +0100) | ||
| tree | c6c17062fef12afc84b4a79f617c1ab04cb18c4f | treesnapshot (tar.gz zip) |
| parent | 272f75e89088c968c861fef516a4ebc70846dcd5 | commitdiff |
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
| hw/intc/arm_gicv3_cpuif.c | diffblobblamehistory |