| commit | 99c7834fba4e5f204a82a1c456de2148b9595135 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 Nov 2020 21:56:04 +0000 (19 21:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Dec 2020 11:44:55 +0000 (10 11:44 +0000) | ||
| tree | 0bd04b6e704a1f0a0c9eab293eac7f03fb7449d9 | treesnapshot (tar.gz zip) |
| parent | 64f863baeedc86590a608e2f1722dd8640aa9431 | commitdiff |
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4). Update the reset value and the code
that handles writes to this register accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4). Update the reset value and the code
that handles writes to this register accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory | |
| target/arm/cpu.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory |