| commit | 98f62e3d5d7cd25b025f8410005cc3898dfa16e9 | |
| author | Hervé Poussineau <hpoussin@reactos.org> | |
| Thu, 18 Aug 2016 07:31:29 +0000 (18 09:31 +0200) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Tue, 13 Sep 2016 17:08:45 +0000 (13 19:08 +0200) | ||
| tree | 71c7eff8ab99e7a56a25163d8dcf144a72e5e053 | treesnapshot (tar.gz zip) |
| parent | a8632434c7e998be1ffe77871a8fc7ab98049cf0 | commitdiff |
lsi: never set DMA FIFO Empty (DFE) bit in DSTAT register
53C895A datasheet says:
"This bit (DFE) is a pure status bit and will not cause an interrupt"
This bit is already auto-generated in lsi_read_reg when reading the DSTAT register.
This fixes IBM RS/6000 7020 firmware, which is:
- resetting the adapter
- enabling all interrupt sources (including DIP, ie interrupts from DSTAT)
- waiting for ISTAT0 to become 0 (including DIP=0, ie no interrupt coming from DSTAT)
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <1471505489-1221-5-git-send-email-hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
53C895A datasheet says:
"This bit (DFE) is a pure status bit and will not cause an interrupt"
This bit is already auto-generated in lsi_read_reg when reading the DSTAT register.
This fixes IBM RS/6000 7020 firmware, which is:
- resetting the adapter
- enabling all interrupt sources (including DIP, ie interrupts from DSTAT)
- waiting for ISTAT0 to become 0 (including DIP=0, ie no interrupt coming from DSTAT)
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <1471505489-1221-5-git-send-email-hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
| hw/scsi/lsi53c895a.c | diffblobblamehistory |