| commit | 97a254b3f03a184136e381c6d9fd80475e1795ac | |
| author | Stafford Horne <shorne@gmail.com> | |
| Fri, 10 Jan 2020 21:28:43 +0000 (11 06:28 +0900) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Fri, 17 Jan 2020 00:50:43 +0000 (16 14:50 -1000) | ||
| tree | 0e2f6c1cadccbb62d061fd88c1c0313a0cbb454a | treesnapshot (tar.gz zip) |
| parent | 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e | commitdiff |
target/openrisc: Fix FPCSR mask to allow setting DZF
The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.
This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.
This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| target/openrisc/fpu_helper.c | diffblobblamehistory |