| commit | 9542c30bcf13c495400d63616dd8dfa825b04685 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 Nov 2020 21:55:59 +0000 (19 21:55 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Dec 2020 11:44:55 +0000 (10 11:44 +0000) | ||
| tree | 28e52be9f96cbcb73579ebaebea27ba6616b72d9 | treesnapshot (tar.gz zip) |
| parent | 0bf0dd4dcbd9fab324700ac6e0cd061cd043de0d | commitdiff |
target/arm: Implement M-profile FPSCR_nzcvqc
v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
like the existing FPSCR, except that it reads and writes only bits
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
permitted.)
Implement the register. Since we don't yet implement MVE, we handle
the QC bit as RES0, with todo comments for where we will need to add
support later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
like the existing FPSCR, except that it reads and writes only bits
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
permitted.)
Implement the register. Since we don't yet implement MVE, we handle
the QC bit as RES0, with todo comments for where we will need to add
support later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/translate-vfp.c.inc | diffblobblamehistory |