| commit | 94bf2658676be00b6f2b4db5d1788122217665b0 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 26 Jun 2018 16:19:10 +0000 (26 09:19 -0700) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 2 Jul 2018 23:56:52 +0000 (3 09:56 +1000) | ||
| tree | 6121b15476d188ea80373a0d32e57f939ba5af6a | treesnapshot (tar.gz zip) |
| parent | 0f3110fa67d3c3405202104f4833f1780e1a32bb | commitdiff |
target/ppc: Use atomic load for LQ and LQARX
Section 1.4 of the Power ISA v3.0B states that both of these
instructions are single-copy atomic. As we cannot (yet) issue
128-bit loads within TCG, use the generic helpers provided.
Since TCG cannot (yet) return a 128-bit value, add a slot within
CPUPPCState for returning the high half of a 128-bit return value.
This solution is preferred to the helper assigning to architectural
registers directly, as it avoids clobbering all TCG live values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Section 1.4 of the Power ISA v3.0B states that both of these
instructions are single-copy atomic. As we cannot (yet) issue
128-bit loads within TCG, use the generic helpers provided.
Since TCG cannot (yet) return a 128-bit value, add a slot within
CPUPPCState for returning the high half of a 128-bit return value.
This solution is preferred to the helper assigning to architectural
registers directly, as it avoids clobbering all TCG live values.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/cpu.h | diffblobblamehistory | |
| target/ppc/helper.h | diffblobblamehistory | |
| target/ppc/mem_helper.c | diffblobblamehistory | |
| target/ppc/translate.c | diffblobblamehistory |