| commit | 88b2fef6c3c3b45ac0dc2196ace7248a09c8e41d | |
| author | Laurent Vivier <laurent@vivier.eu> | |
| Thu, 18 Jan 2018 19:38:41 +0000 (18 20:38 +0100) | ||
| committer | Laurent Vivier <laurent@vivier.eu> | |
| Thu, 25 Jan 2018 15:02:24 +0000 (25 16:02 +0100) | ||
| tree | 3b1acfcbd019e96dd15217f52066fcd314797e02 | treesnapshot (tar.gz zip) |
| parent | 98670d47cd8d63a529ff230fd39ddaa186156f8c | commitdiff |
target/m68k: add MC68040 MMU
Only add MC68040 MMU page table processing and related
registers (Special Status Word, Translation Control Register,
User Root Pointer and Supervisor Root Pointer).
Transparent Translation Registers, DFC/SFC and pflush/ptest
will be added later.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-3-laurent@vivier.eu>
Only add MC68040 MMU page table processing and related
registers (Special Status Word, Translation Control Register,
User Root Pointer and Supervisor Root Pointer).
Transparent Translation Registers, DFC/SFC and pflush/ptest
will be added later.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-3-laurent@vivier.eu>