| commit | 84c2fdc397b6609d1cef76aec2f1367139d1372e | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Tue, 20 Apr 2021 17:49:40 +0000 (20 19:49 +0200) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sun, 2 May 2021 14:49:34 +0000 (2 16:49 +0200) | ||
| tree | 026a408aafdf5dfe159a336eb3ed22cb76d94f44 | treesnapshot (tar.gz zip) |
| parent | bcad139192b0101e3d7ef593144c314bed4cb8c2 | commitdiff |
target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
| target/mips/translate.c | diffblobblamehistory |