| commit | 80e28a41479723ad3d5fb092048b7564995f79ef | |
| author | Nicholas Piggin <npiggin@gmail.com> | |
| Wed, 13 Sep 2023 04:24:08 +0000 (13 14:24 +1000) | ||
| committer | Nicholas Piggin <npiggin@gmail.com> | |
| Fri, 23 Feb 2024 13:24:43 +0000 (23 23:24 +1000) | ||
| tree | 7f98128b114fe044426610f39d925d1317cfbb72 | treesnapshot (tar.gz zip) |
| parent | 19e81ce51e68d9a1e6a317cd3f3e519757d16dfd | commitdiff |
target/ppc: Improve timebase register defines naming
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.
The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
The timebase in ppc started out with the mftb instruction which is like
mfspr but addressed timebase registers (TBRs) rather than SPRs. These
instructions could be used to read TB and TBU at 268 and 269. Timebase
could be written via the TBL and TBU SPRs at 284 and 285.
The ISA changed around v2.03 to bring TB and TBU reads into the SPR
space at 268 and 269 (access via mftb TBR-space is still supported
but will be phased out). Later, VTB was added which is an entirely
different register.
The SPR number defines in QEMU are understandably inconsistently named.
Change SPR 268, 269, 284, 285 to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
| target/ppc/cpu.h | diffblobblamehistory | |
| target/ppc/helper_regs.c | diffblobblamehistory |