| commit | 808bc3b069fdb5fc660f89e6bc7774eeefdc97ea | |
| author | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 8 Feb 2016 23:28:43 +0000 (9 09:28 +1000) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Tue, 16 Feb 2016 22:59:30 +0000 (17 09:59 +1100) | ||
| tree | f472575858ac71eb23b54d2639026fdb25724811 | treesnapshot (tar.gz zip) |
| parent | b7f0bbd2590a22be4c707e27f85e2334158e83aa | commitdiff |
target-ppc: Include missing MMU models for SDR1 in info registers
The HMP command "info registers" produces somewhat different information on
different ppc cpu variants. For those with a hash MMU it's supposed to
include the SDR1, DAR and DSISR registers related to the MMU. However,
the switch is missing a couple of MMU model variants, meaning we will
miss out this information on certain CPUs which should have it.
This patch corrects the oversight. (Really these MMU model IDs need a big
cleanup, but we might as well fix the bug in the interim).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
The HMP command "info registers" produces somewhat different information on
different ppc cpu variants. For those with a hash MMU it's supposed to
include the SDR1, DAR and DSISR registers related to the MMU. However,
the switch is missing a couple of MMU model variants, meaning we will
miss out this information on certain CPUs which should have it.
This patch corrects the oversight. (Really these MMU model IDs need a big
cleanup, but we might as well fix the bug in the interim).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
| target-ppc/translate.c | diffblobblamehistory |