| commit | 7e33517fdd25ce2dc95b22b8afd743a979d8dfb4 | |
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | |
| Thu, 2 Mar 2023 13:37:05 +0000 (2 13:37 +0000) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Tue, 7 Mar 2023 17:39:00 +0000 (7 12:39 -0500) | ||
| tree | df21b5748009ec96516b0e97bb776dce387e96c2 | treesnapshot (tar.gz zip) |
| parent | 47f0e7ab3272737c174ca68c03843e0d1996dc22 | commitdiff |
hw/pci-bridge/cxl_root_port: Wire up MSI
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
| hw/pci-bridge/cxl_root_port.c | diffblobblamehistory |