| commit | 7d6f01a12be534ce2ffaf0aa8741e5f5efca2362 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 30 Nov 2020 10:13:01 +0000 (30 11:13 +0100) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Sun, 13 Dec 2020 18:58:54 +0000 (13 19:58 +0100) | ||
| tree | 2f48e4b400ce240f1b1dffceb06674663b35fc37 | treesnapshot (tar.gz zip) |
| parent | 90c429ee765ec6ca2e2384edc9e45b4ddfae9adb | commitdiff |
target/mips: Allow executing MSA instructions on Loongson-3A4000
The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
Commit af868995e1b correctly set the 'MSA present' bit of Config3
register, but forgot to allow the MSA instructions decoding in
insn_flags, so executing them triggers a 'Reserved Instruction'.
Fix by adding the ASE_MSA mask to insn_flags.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <20201130102228.2395100-1-f4bug@amsat.org>
The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html
Commit af868995e1b correctly set the 'MSA present' bit of Config3
register, but forgot to allow the MSA instructions decoding in
insn_flags, so executing them triggers a 'Reserved Instruction'.
Fix by adding the ASE_MSA mask to insn_flags.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <20201130102228.2395100-1-f4bug@amsat.org>
| target/mips/translate_init.c.inc | diffblobblamehistory |