| commit | 777ab8d84442dd6c0c5fbf787de87779d5ab82e8 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 1 Mar 2022 21:59:48 +0000 (1 11:59 -1000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 2 Mar 2022 19:27:37 +0000 (2 19:27 +0000) | ||
| tree | 5fd24e221ad8c56addbcc50e38a8f402eddee39f | treesnapshot (tar.gz zip) |
| parent | f4ecc01537684a4125c35433f3097295d0a1f839 | commitdiff |
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The original A.a revision of the AArch64 ARM required that we
force-extend the addresses in these registers from 49 bits.
This language has been loosened via a combination of IMPLEMENTATION
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
the entire aligned address.
This means that we do not have to consider whether or not FEAT_LVA
is enabled, and decide from which bit an address might need to be
extended.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/helper.c | diffblobblamehistory |