| commit | 76f4a8aecae7f287d6e7f3b763ae88382c3a5457 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 28 May 2024 20:30:13 +0000 (28 13:30 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 30 May 2024 14:24:38 +0000 (30 15:24 +0100) | ||
| tree | a12f9fc1acf4b07db71013b09f9078f84fdb8918 | treesnapshot (tar.gz zip) |
| parent | b1d592e7b0a7301eae8e3baa99744ac35db3cd2a | commitdiff |
target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB
No need for a full comparison; xor produces non-zero bits
for QC just fine.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
No need for a full comparison; xor produces non-zero bits
for QC just fine.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/tcg/gengvec.c | diffblobblamehistory |