| commit | 702763fa322ea69dde92517735507e0ac3879b5d | |
| author | David Gibson <david@gibson.dropbear.id.au> | |
| Sun, 7 Apr 2013 19:08:20 +0000 (7 19:08 +0000) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Fri, 26 Apr 2013 21:02:41 +0000 (26 23:02 +0200) | ||
| tree | 13dff3f2861c111843819f8c4edcb952054f95e1 | treesnapshot (tar.gz zip) |
| parent | 0cbad81f70546b58f08de3225f1eca7a8b869b09 | commitdiff |
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all
6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an
extra control register (MMCRA). This patch adds stub support for them to
qemu - the registers won't do anything, but with this change won't cause
illegal instruction traps accessing them. They're also registered with
their ONE_REG ids, so their value will be kept in sync with KVM where
appropriate.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
In addition to the performance monitor registers found on nearly all
6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an
extra control register (MMCRA). This patch adds stub support for them to
qemu - the registers won't do anything, but with this change won't cause
illegal instruction traps accessing them. They're also registered with
their ONE_REG ids, so their value will be kept in sync with KVM where
appropriate.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/cpu.h | diffblobblamehistory | |
| target-ppc/translate_init.c | diffblobblamehistory |