| commit | 6c1adc919b6a81e008b919c53902b4877ef4d737 | |
| author | Alexander Graf <agraf@suse.de> | |
| Tue, 17 Dec 2013 19:42:34 +0000 (17 19:42 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 17 Dec 2013 20:12:51 +0000 (17 20:12 +0000) | ||
| tree | edb74edb6dc56584905e243cd18dd773eadf23a8 | treesnapshot (tar.gz zip) |
| parent | 8220e911c240df5b4b2a1473f0ba9feddc154c45 | commitdiff |
target-arm: A64: add support for 2-src shift reg insns
This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| target-arm/translate-a64.c | diffblobblamehistory |