| commit | 6a43e0b6e1f6bcd6b11656967422f4217258200a | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 3 Feb 2016 13:46:33 +0000 (3 13:46 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 3 Feb 2016 13:46:33 +0000 (3 13:46 +0000) | ||
| tree | 810246be506405944d67dace0851d438a60ef29b | treesnapshot (tar.gz zip) |
| parent | a43e68a08bd0d723cc7e480e422a1008a5bb78a9 | commitdiff |
target-arm: Make various system registers visible to EL3
The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ,
SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from
EL3 even if the CPU has no EL2 (unlike some others which are RES0
from EL3 in that configuration). Move them from el2_cp_reginfo[] to
v8_cp_reginfo[] so they are always present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1453227802-9991-1-git-send-email-peter.maydell@linaro.org
The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ,
SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from
EL3 even if the CPU has no EL2 (unlike some others which are RES0
from EL3 in that configuration). Move them from el2_cp_reginfo[] to
v8_cp_reginfo[] so they are always present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1453227802-9991-1-git-send-email-peter.maydell@linaro.org
| target-arm/helper.c | diffblobblamehistory |