| commit | 6508799707bbf018df82d354c388820217757f21 | |
| author | Tao Xu <tao3.xu@intel.com> | |
| Fri, 11 Oct 2019 07:41:03 +0000 (11 15:41 +0800) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Wed, 23 Oct 2019 15:50:27 +0000 (23 17:50 +0200) | ||
| tree | 716cc4415ef040f4324ae5236100a6c5a04d870f | treesnapshot (tar.gz zip) |
| parent | 67192a298f5bf98f96e5516c3b6474c49e4853cd | commitdiff |
target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR
UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR
index E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191011074103.30393-3-tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR
index E1H to determines the maximum time in TSC-quanta that the processor
can reside in either C0.1 or C0.2.
This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
guest.
Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
Message-Id: <20191011074103.30393-3-tao3.xu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| target/i386/cpu.h | diffblobblamehistory | |
| target/i386/kvm.c | diffblobblamehistory | |
| target/i386/machine.c | diffblobblamehistory |