| commit | 64127940aeb674cb5d9d8d0ea4ca20591bf2b010 | |
| author | Bernhard Beschow <shentey@gmail.com> | |
| Sat, 7 Oct 2023 12:38:17 +0000 (7 14:38 +0200) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Sun, 22 Oct 2023 09:18:16 +0000 (22 05:18 -0400) | ||
| tree | fda087bb111d1e600fffc807cf94c76858ddaec4 | treesnapshot (tar.gz zip) |
| parent | 295385127e83a923e166f8b4fe1e543ee4540018 | commitdiff |
hw/isa/piix3: Wire PIC IRQs to ISA bus in host device
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the
interrupts there makes the device model more self-contained. Furthermore, this
allows the ISA interrupts to be wired to internal child devices in
pci_piix3_realize() which will be performed in subsequent patches.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Thie PIIX3 south bridge implements both the PIC and the ISA bus, so wiring the
interrupts there makes the device model more self-contained. Furthermore, this
allows the ISA interrupts to be wired to internal child devices in
pci_piix3_realize() which will be performed in subsequent patches.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20231007123843.127151-10-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| hw/i386/pc_piix.c | diffblobblamehistory | |
| hw/isa/piix3.c | diffblobblamehistory |