target/loongarch: Implement LASX fpu fcvt instructions
commit60df31a2074fccc3ce99c7b758904c6be913ff5a
authorSong Gao <gaosong@loongson.cn>
Thu, 14 Sep 2023 02:26:35 +0000 (14 10:26 +0800)
committerSong Gao <gaosong@loongson.cn>
Wed, 20 Sep 2023 06:33:41 +0000 (20 14:33 +0800)
tree8e5cffdce43b28cdc6ebf71463879f83f39e4c7e
parentc9caf1587a36cd521bb195cc75f43349e446662a
target/loongarch: Implement LASX fpu fcvt instructions

This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFINT.S.L, VFFINT{L/H}.D.W.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-48-gaosong@loongson.cn>
target/loongarch/disas.c
target/loongarch/insn_trans/trans_vec.c.inc
target/loongarch/insns.decode
target/loongarch/vec_helper.c