target-tricore: Fix wrong precedences on psw_write
commit5dc1fbae707513f9664aa88940a2cd52b064cda2
authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Tue, 16 Feb 2016 21:27:32 +0000 (16 22:27 +0100)
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Thu, 25 Feb 2016 11:51:31 +0000 (25 12:51 +0100)
treee9c4aba52ae531b10ba52ab0aaba65b204cc1cf7
parent723733575b90089c51adefde41875310052031c2
target-tricore: Fix wrong precedences on psw_write

Wrong braces on the restore of the cached TCGv SV and V bit could lead to
a wrong PSW. While at this it removes unnecessary braces for the restore
of the cached TCGv AV and SAV bits.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
target-tricore/helper.c