| commit | 5db53e353dfe08492aca793b4748d8182f9780b3 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 28 Feb 2017 12:08:19 +0000 (28 12:08 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 28 Feb 2017 12:08:19 +0000 (28 12:08 +0000) | ||
| tree | 52b101dd3998867f7529ed7a4fc89f8a26dab7cb | treesnapshot (tar.gz zip) |
| parent | e13886e3a790b52f0b2e93cb5e84fdc2ada5471a | commitdiff |
armv7m: Allow SHCSR writes to change pending and active bits
Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Implement the NVIC SHCSR write behaviour which allows pending and
active status of some exceptions to be changed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
| hw/intc/armv7m_nvic.c | diffblobblamehistory |