| commit | 5dad902ce09877a97a6f32e5f6c75b4f8506bd73 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Thu, 7 Mar 2019 22:35:44 +0000 (7 23:35 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Tue, 12 Mar 2019 03:33:04 +0000 (12 14:33 +1100) | ||
| tree | e17c6171757a39c2072a4b3909b9c77dbf5150ac | treesnapshot (tar.gz zip) |
| parent | 90ef386c74b1b2c485b69a1bdb24895bebd45502 | commitdiff |
ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-12-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>