| commit | 5d874e5da23846c40dcb6d73a4c47bb95ff54372 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Fri, 24 May 2024 23:20:20 +0000 (24 16:20 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 28 May 2024 13:29:01 +0000 (28 14:29 +0100) | ||
| tree | ebb72e68d0fb971e146860a85ffde7406b9ee3a5 | treesnapshot (tar.gz zip) |
| parent | c0ca7ed049c468647e9e5239f4275565dcc39179 | commitdiff |
target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/tcg/translate-a64.c | diffblobblamehistory |