| commit | 5d636e21c44ecf982a22a7bc4ca89186079ac283 | |
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | |
| Mon, 4 Jul 2016 12:06:36 +0000 (4 13:06 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 4 Jul 2016 12:15:22 +0000 (4 13:15 +0100) | ||
| tree | f70538ae5e2597eaccf7fe772da04b5397b6b868 | treesnapshot (tar.gz zip) |
| parent | a19861666b574f54c71d1fea9a8d8a84915dfa70 | commitdiff |
hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT
Since QEMU performs cacheable accesses to guest memory when doing DMA
as part of the implementation of emulated PCI devices, guest drivers
should use cacheable accesses as well when running under KVM. Since this
essentially means that emulated PCI devices are DMA coherent, set the
'dma-coherent' DT property on the PCIe host controller DT node.
This brings the DT description into line with the ACPI description,
which already marks the PCI bridge as cache coherent (see commit
bc64b96c984abf).
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 1467134090-5099-1-git-send-email-ard.biesheuvel@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Since QEMU performs cacheable accesses to guest memory when doing DMA
as part of the implementation of emulated PCI devices, guest drivers
should use cacheable accesses as well when running under KVM. Since this
essentially means that emulated PCI devices are DMA coherent, set the
'dma-coherent' DT property on the PCIe host controller DT node.
This brings the DT description into line with the ACPI description,
which already marks the PCI bridge as cache coherent (see commit
bc64b96c984abf).
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 1467134090-5099-1-git-send-email-ard.biesheuvel@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/virt.c | diffblobblamehistory |