arm/translate-a64: initial decode for simd_two_reg_misc_fp16
commit5d432be6fd6efe37833ac82623c3abd35117b421
authorAlex Bennée <alex.bennee@linaro.org>
Thu, 1 Mar 2018 11:05:52 +0000 (1 11:05 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 1 Mar 2018 11:13:59 +0000 (1 11:13 +0000)
treeae5976bc3dab5ff307eabd351ecf676d37a88f82
parent6089030c7322d8f96b54fb9904e53b0f464bb8fe
arm/translate-a64: initial decode for simd_two_reg_misc_fp16

This actually covers two different sections of the encoding table:

   Advanced SIMD scalar two-register miscellaneous FP16
   Advanced SIMD two-register miscellaneous (FP16)

The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions are only
available in the vector form.

This is just the decode skeleton which will be filled out by later
patches.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-17-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c