| commit | 5c10f488ea42dcdd63c8b37792c1e04d69208197 | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Tue, 30 Jun 2020 21:52:25 +0000 (30 14:52 -0700) | ||
| committer | Max Filippov <jcmvbkbc@gmail.com> | |
| Fri, 21 Aug 2020 19:48:16 +0000 (21 12:48 -0700) | ||
| tree | 9e37129ee96a3db4824059e1fe5c3902669142cd | treesnapshot (tar.gz zip) |
| parent | ac81ff227d264b29b8b75068a75d047e2d736d6f | commitdiff |
tests/tcg/xtensa: update test_fp0_conv for DFPU
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| tests/tcg/xtensa/test_fp0_conv.S | diffblobblamehistory |