| commit | 5b7d63706ea460d3999ee9ff3e3e010419d906ca | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Dec 2020 20:14:30 +0000 (10 20:14 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 8 Jan 2021 15:13:38 +0000 (8 15:13 +0000) | ||
| tree | 954b8251d72432e8d8c0d89b0ebe2e9648d04f15 | treesnapshot (tar.gz zip) |
| parent | cc97b0019bb590b9b3c2a623e9ebee48831e0ce3 | commitdiff |
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
The CCR is a register most of whose bits are banked between security
states but where BFHFNMIGN is not, and we keep it in the non-secure
entry of the v7m.ccr[] array. The logic which tries to handle this
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
is zero" requirement; correct the omission.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
The CCR is a register most of whose bits are banked between security
states but where BFHFNMIGN is not, and we keep it in the non-secure
entry of the v7m.ccr[] array. The logic which tries to handle this
bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS
is zero" requirement; correct the omission.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory |