| commit | 5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7 | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Tue, 11 Apr 2017 15:30:00 +0000 (11 17:30 +0200) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Wed, 26 Apr 2017 02:41:55 +0000 (26 12:41 +1000) | ||
| tree | cf13fb73d96ffc293d8318ba8abb0ff290ba5d98 | treesnapshot (tar.gz zip) |
| parent | 4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490 | commitdiff |
ppc/pnv: enable only one LPC bus
The default LPC bus of a multichip system is on chip 0. It's
recognized by the firmware (skiboot) using a "primary" property in the
device tree.
We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of
a chip and set the property directly from the machine level.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The default LPC bus of a multichip system is on chip 0. It's
recognized by the firmware (skiboot) using a "primary" property in the
device tree.
We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of
a chip and set the property directly from the machine level.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/ppc/pnv.c | diffblobblamehistory | |
| hw/ppc/pnv_lpc.c | diffblobblamehistory |