| commit | 59e781fbf13a2dede15437d055b09d7ea120dcac | |
| author | Stefan Markovic <smarkovic@wavecomp.com> | |
| Wed, 3 Oct 2018 12:25:32 +0000 (3 14:25 +0200) | ||
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Thu, 18 Oct 2018 18:37:20 +0000 (18 20:37 +0200) | ||
| tree | 7ab16da6b2b922e8eaa2fa50ec1fc2179b05af3a | treesnapshot (tar.gz zip) |
| parent | 6208f09441dcf8d142ff0e1624ef12da298776a4 | commitdiff |
target/mips: Add availability control for DSP R3 ASE
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| target/mips/internal.h | diffblobblamehistory | |
| target/mips/translate.c | diffblobblamehistory | |
| target/mips/translate_init.inc.c | diffblobblamehistory |