| commit | 59afd43daedabe672c289326a5f268f737d35252 | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Tue, 28 Apr 2020 22:59:08 +0000 (28 15:59 -0700) | ||
| committer | Max Filippov <jcmvbkbc@gmail.com> | |
| Thu, 30 Apr 2020 11:37:36 +0000 (30 04:37 -0700) | ||
| tree | 5e05536b197aa12ee9d984bd18527f910f322604 | treesnapshot (tar.gz zip) |
| parent | 648db19685b7030aa558a4ddbd3a8e53d8c9a062 | commitdiff |
target/xtensa: work around missing SR definitions
Xtensa configuration overlays for recent releases may have special
registers for which [rwx]sr opcodes are defined, but they are not listed
as SR in xtensa_sysreg_name and associated functions. As a result
generic translate_[rwx]sr* functions generate access to uninitialized
cpu_SR causing segfault at runtime.
Don't try to access cpu_SR for such registers, ignore writes and return
0 for reads.
Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Xtensa configuration overlays for recent releases may have special
registers for which [rwx]sr opcodes are defined, but they are not listed
as SR in xtensa_sysreg_name and associated functions. As a result
generic translate_[rwx]sr* functions generate access to uninitialized
cpu_SR causing segfault at runtime.
Don't try to access cpu_SR for such registers, ignore writes and return
0 for reads.
Cc: qemu-stable@nongnu.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| target/xtensa/translate.c | diffblobblamehistory |